SN74LVC573A-Q1_15 Datasheet, PDF (1/15 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74LVC573A-Q1
www.ti.com ............................................................................................................................................... SCAS714B – SEPTEMBER 2003 – REVISED APRIL 2008
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
FEATURES
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• Qualified for Automotive Applications
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 6.9 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce) < 0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at
V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V V_CC)
• I_off Supports Partial-Power-Down Mode
Operation
DW OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
DESCRIPTION/ORDERING INFORMATION
The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers,
and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 125°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER
SOIC – DW
Reel of 2000
SN74LVC573AQDWRQ1
TSSOP – PW
Reel of 2000
SN74LVC573AQPWRQ1
TOP-SIDE MARKING
L573AQ1
L573AQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
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