SN74LVC2G32_15 Datasheet, PDF (1/22 Pages) Texas Instruments – Dual 2-Input Positive-OR Gate

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SN74LVC2G32
SCES201N – APRIL 1999 – REVISED SEPTEMBER 2015
SN74LVC2G32 Dual 2-Input Positive-OR Gate
1 Features
•1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Maximum t_pd of 3.8 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the V_CC
Level
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
3 Description
This dual 2-input positive-OR gate is designed for
1.65-V to 5.5-V V_CC operation.
The SN74LVC2G32 device performs the Boolean
function Y + A ) B or Y + A • B in positive logic.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE
SN74LVC2G32DCT SSOP (8)
2.95 mm × 2.80 mm
SN74LVC2G32DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G32YZP DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Down Translation
• Logical OR
Logic Diagram (Positive Logic)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.