SN74LVC2G241_17 Datasheet, PDF (1/24 Pages) Texas Instruments – Dual Buffer and Driver With 3-State Outputs

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SN74LVC2G241
SCES210O – APRIL 1999 – REVISED DECEMBER 2015
SN74LVC2G241 Dual Buffer and Driver With 3-State Outputs
1 Features
•1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.1 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down
to the V_CC Level
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• AV Receivers
• Blu-ray Players and Home Theaters
• DVD Recorders and Players
• Desktop or Notebook PCs
• Digital Radio or Internet Radio Players
• Digital Video Cameras (DVC)
• Embedded PCs
• GPS: Personal Navigation Devices
• Mobile Internet Devices
• Network Projector Front-Ends
• Portable Media Players
• Pro Audio Mixers
3 Description
This dual buffer and line driver is designed for 1.65-V
to 5.5-V V_CC operation.
The SN74LVC2G241 device is designed specifically
to improve both the performance and density of 3-
state memory-address drivers, clock drivers, and bus-
oriented receivers and transmitters.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
The SN74LVC2G241 device is organized as two 1-bit
line drivers with separate output-enable (1OE, 2OE)
inputs. When 1OE is low and 2OE is high, the device
passes data from the A inputs to the Y outputs. When
1OE is high and 2OE is low, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to V_CC through a
pullup resistor, and OE should be tied to GND
through a pulldown resistor; the minimum value of the
resistor is determined by the current-sinking or the
current-sourcing capability of the driver.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC2G241DCT SM8 (8)
2.95 mm × 2.80 mm
SN74LVC2G241DCU VSOOP (8)
2.30 mm × 2.00 mm
SN74LVC2G241YZP DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.