SN74LVC1T45-Q1_14 Datasheet, PDF (1/21 Pages) Texas Instruments – SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER

SN74LVC1T45-Q1
www.ti.com
SCES677B – SEPTEMBER 2006 – REVISED SEPTEMBER 2012
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
Check for Samples: SN74LVC1T45-Q1
FEATURES
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• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
• Customer-Specific Configuration Control Can
Be Supported Along With Major-Change
Approval
• Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.65-V to
5.5-V Power-Supply Range
• V_CC Isolation Feature – If Either V_CC Input Is at
GND, Both Ports Are in the High-Impedance
State
• DIR Input Circuit Referenced to V_CCA
• ±24-mA Output Drive at 3.3 V
• I_off Supports Partial-Power-Down Mode
Operation
• Maximum Data Rates
– 420 Mbps (3.3-V to 5-V Translation)
– 210 Mbps (Translate to 3.3 V)
– 140 Mbps (Translate to 2.5 V)
– 75 Mbps (Translate to 1.8 V)
APPLICATIONS
• Automotive
• Logic Applications
DCK PACKAGE
(TOP VIEW)
V_CCA
1
6
V_CCB
GND 2
5
DIR
A
3
4
B
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track V_CCA. V_CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track
V_CCB. V_CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC1T45-Q1 is designed for asynchronous communication between two data buses. The logic levels
of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits
data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when
the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess I_CC and I_CCZ.
The SN74LVC1T45-Q1 is designed so that the DIR input is powered by V_CCA.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance
state.
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PRODUCTION DATA information is current as of publication date.
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