SN74LVC1G79-EP Datasheet, PDF (1/11 Pages) Texas Instruments – SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74LVC1G79-EP
www.ti.com....................................................................................................................................................... SCES646A – AUGUST 2005 – REVISED APRIL 2009
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
FEATURES
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• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 5 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Military (–55°C/125°C)
Temperature Range⁽¹⁾
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
DCK PACKAGE
(TOP VIEW)
D
1
5
V_CC
CLK
2
GND
3
4Q
See mechanical drawings for dimensions.
(1) Additional temperature ranges are available - contact factory
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting
the level at the output.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–55°C to 115°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
SOT (SC-70) – DCK
Reel of 3000 SN74LVC1G79WDCKREP
TOP-SIDE MARKING⁽²⁾
CR_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCK: The actual top-side marking has one additional character that designates the assembly/test site.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2009, Texas Instruments Incorporated