SN74LVC1G374-Q1 Datasheet, PDF (1/12 Pages) Texas Instruments –
SINFLE D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

D Qualified for Automotive Applications
D Supports 5-V V_CC Operation
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 4 ns at 3.3 V
D Low Power Consumption, 10-µA Max I_CC
D ±24-mA Output Drive at 3.3 V
D I_off Supports Partial-Power-Down Mode
Operation
SN74LVC1G374ĆQ1
SINGLE DĆTYPE FLIPĆFLOP
WITH 3ĆSTATE OUTPUT
SCES607A − SEPTEMBER 2004 − REVISED APRIL 2008
D Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE
(TOP VIEW)
description/ordering information
This single D-type flip-flop is designed for 1.65-V to
5.5-V V_CC operation.
The SN74LVC1G374 features a 3-state output
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
input/output (I/O) ports, bidirectional bus drivers, and
working registers.
CLK ¹
GND ²
D³
6 _OE
5 _VCC
4_Q
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D)
input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION^{
TA
PACKAGE^}
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING^§
SOT (SOT-23) − DBV
−40°C to 125°C
SOT (SC-70) − DCK
Reel of 3000
Reel of 3000
SN74LVC1G374QDBVRQ1 CA40
SN74LVC1G374QDCKRQ1 D40
† _{For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see}
the TI web site at http://www.ti.com.
}Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ _{DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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