SN74LVC1G373_15 Datasheet, PDF (1/20 Pages) Texas Instruments – Single D-Type Latch With 3-State Output

SN74LVC1G373
www.ti.com
SCES528D – DECEMBER 2003 – REVISED DECEMBER 2013
Single D-Type Latch With 3-State Output
Check for Samples: SN74LVC1G373
FEATURES
1
•2 Available in the Texas Instruments NanoFree™
Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to V_CC
• Max t_pd of 4 ns at 3.3 V
• Low Power Consumption, 10-μA Max I_CC
• ±24-mA Output Drive at 3.3 V
• I_off Supports Live Insertion, Partial-Power-
Down Mode, and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This single D-type latch is designed for 1.65-V to 5.5-
V V_CC operation.
The SN74LVC1G373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. While the latch-
enable (LE) input is high, the Q outputs follow the
data (D) inputs. When LE is taken low, the Q outputs
are latched at the logic levels set up at the D inputs.
While the latch-enable (LE) input is high, the Q output
follows the data (D) input. When LE is taken low, the
Q output is latched at the logic level set up at the D
input.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
OE does not affect the internal operations of the
latch. Old data can be retained or new data can be
entered while the outputs are in the high-impedance
state.
A buffered output-enable (OE) input can be used to
place the output in either a normal logic state (high or
low logic levels) or the high-impedance state. In the
high-impedance state, the output neither loads nor
drives the bus lines significantly. The high-impedance
state and increased drive provide the capability to
drive bus lines without interface or pullup
components.
To ensure the high-impedance state during power up
or power down, OE should be tied to V_CC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
LE
1
GND
2
6
OE
LE
1
6 OE
D ³⁴ Q
GND ^{2 5 V}_CC
GND
2
5
V_CC
LE ^{1 6} OE
5
V_CC
D
3
4Q
D
3
4
Q
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated