SN74LVC1G32-EP Datasheet, PDF (1/15 Pages) Texas Instruments – SINGLE 2-INPUT POSITIVE-OR GATE

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FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of –55°C
to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 3.6 ns at 3.3 V
• Low Power Consumption, 10 μA Max I_CC
• ±24-mA Output Drive at 3.3 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC1G32-EP
SINGLE 2-INPUT POSITIVE-OR GATE
SCES458D – DECEMBER 2003 – REVISED JUNE 2007
• I_off Supports Partial Power Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE
(TOP VIEW)
A1
B2
GND 3
5 V_CC
4Y
DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V V_CC operation.
The SN74LVC1G32 performs the Boolean function Y + A ) B or Y + A • B in positive logic.
This device is fully specified for partial power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
–55°C to 125°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER
SOT (SC-70) – DCK Reel of 3000
SN74LVC1G32IDCKREP
SOT (SC-70) – DCK Reel of 3000
SN74LVC1G32MDCKREP
SOP (SOT-23) – DBV Reel of 3000
SN74LVC1G32MDBVREP
TOP-SIDE MARKING⁽³⁾
CG0
BYB
SBGM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(3) The actual top-side making has one additional character that designates the wafer fab/assembly site.
FUNCTION TABLE
INPUTS
A
B
H
X
X
H
L
L
OUTPUT
Y
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated