SN74LVC1G123_15 Datasheet, PDF (1/26 Pages) Texas Instruments – Single Retriggerable Monostable Multivibrator

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SN74LVC1G123
SCES586D – JULY 2004 – REVISED JUNE 2015
SN74LVC1G123 Single Retriggerable Monostable Multivibrator
With Schmitt-Trigger Inputs
1 Features
•1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 8 ns at 3.3 V
• Supports Mixed-Mode Voltage Operation on
All Ports
• Supports Down Translation to V_CC
• Schmitt-Trigger Circuitry on A and B Inputs for
Slow Input Transition Rates
• Edge Triggered From Active-High or Active-Low
Gated Logic Inputs
• Retriggerable for Very Long Output Pulses, Up to
100% Duty Cycle
• Overriding Clear Terminates Output Pulse
• Glitch-Free Power-Up Reset on Outputs
• I_off Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• AV Receivers
• Blu-ray Players and Home Theaters
• DVD Recorders and Players
• Desktop PCs or Notebook PCs
• Digital Radio and Internet Radio Players
• Digital Video Cameras (DVC)
• Embedded PCs
• GPS: Personal Navigation Devices
• Mobile Internet Devices
• Network Attached Storage (NAS)
• Personal Digital Assistant (PDA)
• Server PSU
• Solid-State Drive (SSD): Client and Enterprise
• Video Analytics Servers
• Wireless Headsets, Keyboards, and Mice
3 Description
The SN74LVC1G123 device is a single retriggerable
monostable multivibrator designed for 1.65-V to 5.5-V
V_CC operation.
This monostable multivibrator features output pulse-
duration control by three methods. In the first method,
the A input is low, and the B input goes high. In the
second method, the B input is high, and the A input
goes low. In the third method, the A input is low, the
B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting
external resistance and capacitance values. The
external timing capacitor must be connected between
C_ext and R_ext/C_ext (positive) and an external resistor
connected between R_ext/C_ext and V_CC. To obtain
variable pulse durations, connect an external variable
resistance between R_ext/C_ext and V_CC. The output
pulse duration also can be reduced by taking CLR
low.
Pulse triggering occurs at a particular voltage level
and is not directly related to the transition time of the
input pulse. The A and B inputs have Schmitt triggers
with sufficient hysteresis to handle slow input
transition rates with jitter-free triggering at the
outputs.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SSOP (8)
2.95 mm × 2.80 mm
SN74LVC1G123
VSSOP (8)
2.30 mm × 2.00 mm
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A1
7 _Rext/Cext
6
C_ext
2
B
5
Q
CLR ³
R
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.