SN74LVC16373A-EP Datasheet, PDF (1/10 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS825 – JUNE 2006
FEATURES
• Member of the Texas Instruments Widebus™
Family
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.2 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V
at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode
Operation
• Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/
ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V V_CC operation.
The SN74LVC16373A is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. The device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
DL PACKAGE
(TOP VIEW)
1OE ¹
1Q1 ²
1Q2 ³
GND ⁴
1Q3 ⁵
1Q4 ⁶
V_CC ⁷
1Q5 ⁸
1Q6 ⁹
GND ¹⁰
1Q7 ¹¹
1Q8 ¹²
2Q1 ¹³
2Q2 ¹⁴
GND ¹⁵
2Q3 ¹⁶
2Q4 ¹⁷
V_CC ¹⁸
2Q5 ¹⁹
2Q6 ²⁰
GND ²¹
2Q7 ²²
2Q8 ²³
2OE ²⁴
48 _1LE
47 _1D1
46 _1D2
45 _GND
44 _1D3
43 _1D4
42 _VCC
41 _1D5
40 _1D6
39 _GND
38 _1D7
37 _1D8
36 _2D1
35 _2D2
34 _GND
33 _2D3
32 _2D4
31 _VCC
30 _2D5
29 _2D6
28 _GND
27 _2D7
26 _2D8
25 _2LE
A buffered output-enable (OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide
the capability to drive bus lines without interface or
pullup components.
ORDERING INFORMATION
T_A
–55°C to 125°C SSOP – DL
PACKAGE ⁽¹⁾
Tape and reel
ORDERABLE PART NUMBER
CLVC16373AMDLREP
TOP-SIDE MARKING
LVC16373AMEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated