SN74LV8154-EP Datasheet, PDF (1/15 Pages) Texas Instruments – DUAL 16 BIT BINARY COUNTER WITH 3-STATE OUTPUT REGISTERS

D Controlled Baseline
− One Assembly Site
− One Test Site
− One Fabrication Site
D Extended Temperature Performance of
−55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Can Be Used as Two 16 Bit Counters or a
Single 32 Bit Counter
D 2-V to 5.5-V V_CC Operation
D Max t_pd of 25 ns at 5 V (RCLK to Y)
D Typical V_OLP (Output Ground Bounce)
<0.7 V at V_CC = 5 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>4.4 V at V_CC = 5 V, T_A = 25°C
D I_off Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN74LV8154ĆEP
DUAL 16 BIT BINARY COUNTER
WITH 3ĆSTATE OUTPUT REGISTERS
SCLS704A − JULY 2006 − REVISED SEPTEMBER 2007
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
PW PACKAGE
(TOP VIEW)
CLKA 1
CLKB 2
GAL 3
GAU 4
GBL 5
GBU 6
RCLK 7
RCOA 8
CLKBEN 9
GND 10
20 V_CC
19 Y0
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 CCLR
description/ordering information
The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V V_CC
operation.
This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an
upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be
output at Y0−Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the
A and B storage registers. All three clock signals are positive-edge triggered.
A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.
To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied
to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability
of the driver.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION^†
TA
PACKAGE^}
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°C TSSOP − PW Tape and reel SN74LV8154MPWREP LV8154ME
† _{For the most current package and ordering information, see the Package Option Addendum at the}
end of this document, or see the TI website at www.ti.com.
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2007, Texas Instruments Incorporated
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