SN74LV74A-EP Datasheet, PDF (1/14 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS696 – JANUARY 2006
FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of– 55°C
to 125°C
• Enhanced Diminishing Manufacturing
Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• 2-V to 5.5-V V_CC Operation
• Max t_pd of 13 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Voltage Operation on
All Ports
• I_off Supports Partial-Power-Down Mode
Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
1CLR ₁
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
14 ^VCC
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8 2Q
DESCRIPTION/ORDERING INFORMATION
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V V_CC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION
T_A
–55°C to 125°C
PACKAGE ⁽¹⁾
TSSOP – PW
Reel of 2000
ORDERABLE PART NUMBER
SN74LV74AMPWREP
TOP-SIDE MARKING
LV74AEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains ADVANCE
INFORMATION on new products in the sampling or preproduction
phase of development. Characteristic data and other specifications
are subject to change without notice.
Copyright © 2006, Texas Instruments Incorporated