SN74LV595A Datasheet, PDF (1/30 Pages) Texas Instruments – 8-Bit Shift Registers With 3-State Output Registers

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SN74LV595A
SCLS414Q – APRIL 1998 – REVISED APRIL 2016
SN74LV595A 8-Bit Shift Registers With 3-State Output Registers
1 Features
•1 2-V to 5.5-V V_CC Operation
• Max t_pd of 7.1 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
• Support Mixed-Mode Voltage Operation on All
Ports
• 8-Bit Serial-In, Parallel-Out Shift
• I_off Supports Live Insertion, Partial Power-Down
Mode, and Back-Drive Protection
• Shift Register Has Direct Clear
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
2 Applications
• Network Switches
• Power Infrastructures
• PCs and Notebooks
• LED Displays
• Servers
• I/O Expanders
3 Description
The SN74LV595A device contains an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Both the shift register clock (SRCLK)
and storage register clock (RCLK) are positive-edge
triggered.
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
VQFN (16)
4.00 mm × 3.50 mm
SNx4LV595A
TSSOP (16)
SOP (16)
5.00 mm × 4.40 mm
10.20 mm × 5.30 mm
SOIC (16)
9.00 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
OE
RCLK
SRCLR
SRCLK
SER
1D Q
3D
C1
C3 Q
QA
R
2D Q
3D
C2
C3 Q
QB
R
2D Q
3D
C2
C3 Q
QC
R
2D Q
3D
C2
C3 Q
QD
R
2D Q
3D
C2
C3 Q
QE
R
2D Q
3D
C2
C3 Q
QF
R
2D Q
3D
C2
C3 Q
QG
R
2D Q
C2
R
3D
C3 Q
QH
QH′
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.