SN74LV393A-EP Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL 4-BIT BINARY COUNTER

SN74LV393AĆEP
DUAL 4ĆBIT BINARY COUNTER
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D 2-V to 5.5-V V_CC Operation
D Max t_pd of 14.5 ns at 5 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SCLS566A − JANUARY 2004 − REVISED MAY 2004
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D I_off Supports Partial-Power-Down-Mode
Operation
D Dual 4-Bit Binary Counters With Individual
Clocks
D Direct Clear for Each 4-Bit Counter
D Can Significantly Improve System
Densities by Reducing Counter Package
Count by 50 Percent
PW PACKAGE
(TOP VIEW)
1CLK 1
1CLR 2
1Q_A 3
1Q_B 4
1Q_C ⁵
1Q_D ⁶
GND ⁷
14 V_CC
13 2CLK
12 2CLR
11 2Q_A
10 _2QB
9 _2QC
8 _2QD
description/ordering information
The SN74LV393A contains eight flip-flops and additional gating to implement two individual 4-bit counters in
a single package. This device is designed for 2-V to 5.5-V V_CC operation.
This device comprises two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)
input. The device changes state on the negative-going transition of the CLK pulse. N-bit binary counters can
be implemented with each package, providing the capability of divide by 256. The SN74LV393A has parallel
outputs from each counter stage so that any submultiple of the input count frequency is available for system
timing signals.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV393ATPWREP LV393EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
CLK CLR
FUNCTION
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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