SN74LV374AT Datasheet, PDF (1/21 Pages) Texas Instruments – OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74LV374AT
www.ti.com
SCES632 – JUNE 2010
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Check for Samples: SN74LV374AT
FEATURES
1
• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V V_CC Operation
• Typical t_pd of 4.9 ns at 5 V
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 5 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2.3 V
at V_CC = 5 V, T_A = 25°C
• Support Mixed-Mode Voltage Operation on All
Ports
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
10
20
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11
DESCRIPTION
The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated