SN74LV125PWLE Datasheet, PDF (1/7 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

D EPIC ( Enhanced-Performance Implanted
CMOS) 2-µ Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC, T_A = 25°C
D ESD Protection Exceeds 2000 V per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These quadruple bus buffer gates are designed
for 2.7-V to 5.5-V V_CC operation.
The ’LV125 feature independent line drivers with
3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
The SN54LV125 is characterized for operation
over the full military temperature range of −55°C
to 125°C. The SN74LV125 is characterized for
operation from −40°C to 85°C.
SN54LV125, SN74LV125
QUADRUPLE BUS BUFFER GATES
WITH 3ĆSTATE OUTPUTS
SCES003B − NOVEMBER 1994 − REVISED APRIL 1996
SN54LV125 . . . J OR W PACKAGE
SN74LV125 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
1OE ₁
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 ^V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
SN54LV125 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2OE
NC
2A
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
NC − No internal connection
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  1996, Texas Instruments Incorporated
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