SN74LV123A-EP Datasheet, PDF (1/12 Pages) Texas Instruments – DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS

SN74LV123AĆEP
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
WITH SCHMITTĆTRIGGER INPUTS
SCLS498A − MAY 2003 − REVISED MAY 2004
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
D Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D I_off Supports Partial-Power-Down Mode
Operation
D Retriggerable for Very Long Output Pulses,
Up To 100% Duty Cycle
D Overriding Clear Terminates Output Pulse
D Glitch-Free Power-Up Reset on Outputs
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
1A 1
1B 2
1CLR 3
1Q 4
2Q 5
2C_ext 6
2R_ext/C_ext 7
GND ⁸
16 ^V_CC
15 1R_ext/C_ext
14 1C_ext
13 1Q
12 2Q
11 2CLR
10 2B
9 2A
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V V_CC operation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method,
the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes
low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor
connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable
resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV123ATPWREP L123AEP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2004, Texas Instruments Incorporated
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