SN74LV11A-Q1 Datasheet, PDF (1/10 Pages) Texas Instruments – TRIPLE 3-INPUT POSITIVE-AND GATE

SN74LV11A-Q1
TRIPLE 3-INPUT POSITIVE-AND GATE
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D 2-V to 5.5-V V_CC Operation
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC= 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D I_off Supports Partial-Power-Down Mode
Operation
SCES468D − JULY 2003 − REVISED JANUARY 2008
PW PACKAGE
(TOP VIEW)
1A ¹
1B ²
2A ³
2B ⁴
2C ⁵
2Y ⁶
GND ⁷
14 V_CC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
description/ordering information
This triple 3-input positive-AND gate is designed for 2-V to 5.5-V V_CC operation.
The SN74LV11A performs the Boolean function Y + A • B • C or Y + A ) B ) C in positive logic.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION^†
T_A
PACKAGE^‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV11ATPWRQ1 LV11AT
† _{For the most current package and ordering information, see the Package Option Addendum at the end}
of this document, or see the TI web site at www.ti.com.
‡ _{Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.}
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
H
L
X
X
L
X
L
X
L
X
X
L
L
logic diagram, each gate (positive logic)
A
B
Y
C
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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