SN74LV08A-Q1 Datasheet, PDF (1/10 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-AND GATE

SN74LV08A-Q1
QUADRUPLE 2-INPUT POSITIVE-AND GATE
D Qualified for Automotive Applications
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D I_off Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCLS465C − FEBRUARY 2003 − REVISED JANUARY 2008
PW PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y ⁶
GND ⁷
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 _3A
8 _3Y
description/ordering information
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V V_CC operation.
The SN74LV08A performs the Boolean function Y + A • B or Y + A ) B in positive logic.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION^†
T_A
PACKAGE^‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV08ATPWRQ1 LV08ATQ
† _{For the most current package and ordering information, see the Package Option Addendum at the end}
of this document, or see the TI web site at http://www.ti.com.
‡ _{Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.}
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2008, Texas Instruments Incorporated
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