SN74LV08A-EP Datasheet, PDF (1/9 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-AND GATE

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FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of
–55°C to 125°C
• Enhanced Diminishing Manufacturing
Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Voltage Operation on
All Ports
• I_off Supports Partial-Power-Down Mode
Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LV08A-EP
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCLS481B – MAY 2003 – REVISED JANUARY 2006
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V V_CC operation.
The SN74LV08A-EP performs the Boolean function Y = A S B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T_A
–40°C to 105°C
–55°C to 125°C
PACKAGE ⁽¹⁾
TSSOP – PW
Tape and reel
TSSOP – PW
Tape and reel
ORDERABLE PART NUMBER
SN74LV08ATPWREP
SN74LV08AMPWREP
TOP-SIDE MARKING
LV08AEP
LV08AEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
H
L
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated