SN74HC166A-EP Datasheet, PDF (1/13 Pages) Texas Instruments – 8-BIT PARALLEL-LOAD SHIFT REGISTER

SN74HC166AĆEP
8ĆBIT PARALLELĆLOAD SHIFT REGISTER
SCLS559 − JANUARY 2004
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max I_CC
D Typical t_pd = 13 ns
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Synchronous Load
D Direct Overriding Clear
D Parallel-to-Serial Conversion
D OR PW PACKAGE
(TOP VIEW)
SER ₁
A2
B3
C4
D5
CLK INH 6
CLK 7
GND 8
16 ^V_CC
15 SH/LD
14 H
13 Q_H
12 G
11 F
10 E
9 CLR
description/ordering information
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high,
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D
TSSOP − PW
Tape and reel
Tape and reel
SN74HC166AIDREP
SN74HC166AIPWREP§
SHC166IEP
SHC166IEP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
§ _{Product Preview}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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