SN74GTLPH306_15 Datasheet, PDF (1/17 Pages) Texas Instruments – 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER

www.ti.com
FEATURES
• TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
• LVTTL Interfaces Are 5-V Tolerant
• Medium-Drive GTLP Outputs (50 mA)
• LVTTL Outputs (–24 mA/24 mA)
• GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
• I_off and Power-Up 3-State Support Hot
Insertion
• Bus Hold on A-Port Data Inputs
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED APRIL 2005
DGV, DW, OR PW PACKAGE
(TOP VIEW)
OE 1
V_CC 2
A1 3
A2 4
A3 5
A4 6
GND 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 DIR
23 V_REF
22 B1
21 B2
20 B3
19 B4
18 GND
17 B5
16 B6
15 B7
14 B8
13 GND
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard
LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input
threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and
TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models.
The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance
down to 19 Ω.
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD
8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V_TT = 1.2 V and V_REF = 0.8 V) or GTLP (V_TT = 1.5 V and
V_REF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V_REF is the B-port differential input
reference voltage.
This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated