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SN74GTL2003 Datasheet, PDF (1/20 Pages) Texas Instruments – 8-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
SN74GTL2003
www.ti.com
SCDS305 – FEBRUARY 2011
8-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
Check for Samples: SN74GTL2003
FEATURES
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• Provides Bidirectional Voltage Translation
With No Direction Control Required
• Allows Voltage Level Translation From 1 V up
to 5 V
• Provides Direct Interface With GTL, GTL+,
LVTTL/TTL, and 5-V CMOS Levels
• Low On-State Resistance Between Input and
Output Pins (Sn/Dn)
• Supports Hot Insertion
• No Power Supply Required – Will Not Latch Up
• 5-V-Tolerant Inputs
• Low Standby Current
• Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
APPLICATIONS
• Bidirectional or Unidirectional Applications
Requiring Voltage-Level Translation From Any
Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
• Low Voltage Processor I2C Port Translation to
3.3-V and/or 5-V I2C Bus Signal Levels
• GTL/GTL+ Translation to LVTTL/TTL Signal
Levels
terminal 1
index area
QFN PACKAGE
(TOP VIEW)
SREF 2
S1 3
S2 4
S3 5
S4 6
S5 7
S6 8
S7 9
19 DREF
18 D1
17 D2
16 D3
15 D4
14 D5
13 D6
12 D7
PW PACKAGE
(TOP VIEW)
GND 1
SREF 2
S1 3
S2 4
S3 5
S4 6
S5 7
S6 8
S7 9
S8 10
20 GREF
19 DREF
18 D1
17 D2
16 D3
15 D4
14 D5
13 D6
12 D7
11 D8
DESCRIPTION/ORDERING INFORMATION
The SN74GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a
reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage
translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between
the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on
the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port
is pulled to VCC by the pullup resistors.
All transistors in the SN74GTL2003 have the same electrical characteristics, and there is minimal deviation from
one output to another in voltage or propagation delay. This offers superior matching over discrete transistor
voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being
identical, the reference transistor (SREF/DREF) can be located on any of the other eight matched Sn/Dn
transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides
excellent ESD protection.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2011, Texas Instruments Incorporated