SN74F323 Datasheet, PDF (1/8 Pages) Texas Instruments – 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

SN74F323
8ĆBIT UNIVERSAL SHIFTĆSTORAGE REGISTER
WITH SYNCHRONOUS CLEAR AND 3ĆSTATE OUTPUTS
SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993
• Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
• Operates With Outputs Enabled or at High
Impedance
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N-Bit Word Lengths
• Synchronous Clear
• Applications:
Stacked or Push-Down Registers
Buffer Storage
Accumulator Registers
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
DW OR N PACKAGE
(TOP VIEW)
S0 1
OE1 2
OE2 3
G/Q_G 4
E/Q_E 5
C/Q_C 6
A /Q_A 7
Q_A′ 8
CLR ⁹
GND ¹⁰
20 V_CC
19 S1
18 SL
17 Q_H′
16 H/Q_H
15 F/Q_F
14 D/Q_D
13 B/Q_B
12 _CLK
11 _SR
description
This 8-bit universal register features multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin
package. Two function-select (S0, S1) and two output-enable (OE1, OE2) inputs can be used to choose the
modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register.
Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but this
has no effect on clearing, shifting, or storage of data.
The SN74F323 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
MODE _{CLR S1 S0 OE1† OE2† CLK SL SR A /QA B/QB}
L XL L
L
↑ XX L
L
C/QC
L
I/O PORTS
D/QD E/QE
L
L
F/QF
L
G/QG H/QH
L
L
OUTPUTS
QA_′ QH_′
L
L
Clear L L X L
L
↑ XX L
L
L
L
L
L
L
L
L
L
L HH X
X
↑ XX X
X
X
X
X
X
X
X
L
L
H LL L
Hold
H XX L
Shift ^{H L H L}
Right _{H L H L}
Shift ^{H H L L}
Left _{H H L L}
Load H H H X
L
X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
L
L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
L
↑ X H H QAn QBn QCn QDn QEn QFn QGn H QGn
L
↑ XL
L
QAn QBn QCn QDn QEn QFn QGn L QGn
L
↑ H X QBn QCn QDn QEn QFn QGn QHn H QBn H
L
↑ L X QBn QCn QDn QEn QFn QGn QHn L QBn L
X
↑ XX a
b
c
d
e
f
g
h
a
h
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. These data inputs are loaded into the flip-flops while the
flip-flop outputs are isolated from the I/O terminals.
† _{When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation}
or clearing of the register is not affected.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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