SN74F126_14 Datasheet, PDF (1/12 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74F126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS017B – JANUARY 1989 – REVISED NOVEMBER 2002
D 4.5-V to 5.5-V V_CC Operation
D Max t_pd of 6.5 ns at 5 V
D 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
description/ordering information
The SN74F126 bus buffer features independent
line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
D, N, OR NS PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74F126N
SN74F126N
0°C to 70°C SOIC – D
Tube
Tape and reel
SN74F126D
SN74F126DR
F126
SOP – NS
Tape and reel
SN74F126NSR
74F126
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2002, Texas Instruments Incorporated
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