SN74F112NSR Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The SN74F112 contains two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the setup
time requirements is transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. The SN74F112 can perform
as a toggle flip-flop by tying J and K high.
D OR N PACKAGE
(TOP VIEW)
1CLK 1
1K 2
1J 3
1PRE 4
1Q 5
1Q ⁶
2Q ⁷
GND ⁸
16 V_CC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 _2Q
The SN74F112 is characterized for operation from
0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
↓
L
L
Q0 Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
Toggle
H
H
H
X
X
Q0 Q0
† _{The output levels in this configuration are not guaranteed to}
meet the minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1993, Texas Instruments Incorporated
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