SN74CBTLV3857_15 Datasheet, PDF (1/10 Pages) Texas Instruments – LOW-VOLTAGE 10-BIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS

D Enable Signal Is SSTL_2 Compatible
D Flow-Through Architecture Optimizes PCB
Layout
D Designed for Use With 200 Mbit/s Double
Data-Rate (DDR) SDRAM Applications
D Switch On-State Resistance Is Designed to
Eliminate Series Resistor to DDR SDRAM
D Internal 10-kΩ Pulldown Resistors to
Ground on B Port
D Internal 50-kΩ Pullup Resistor on
Output-Enable Input
D Rail-to-Rail Switching on Data I/O Ports
D I_off Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
SN74CBTLV3857
LOWĆVOLTAGE 10ĆBIT FET BUS SWITCH
WITH INTERNAL PULLDOWN RESISTORS
SCDS085E − OCTOBER 1998 − REVISED OCTOBER 2003
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
V_REF 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
A9 10
A10 11
GND 12
24 V_CC
23 OE
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 B10
description/ordering information
This 10-bit FET bus switch is designed for 3-V to 3.6-V V_CC operation and SSTL_2 output-enable (OE) input
levels.
When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is
open, and the high-impedance state exists between the two ports. There are 10-kΩ pulldown resistors to ground
on the B port.
The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2
data path.
This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP − DBQ Tape and reel SN74CBTLV3857DBQR CL857
SOIC − DW
−40°C to 85°C
Tube
Tape and reel
SN74CBTLV3857DW
SN74CBTLV3857DWR
CBTLV3857
TSSOP − PW Tape and reel SN74CBTLV3857PWR CL857
TVSOP − DGV Tape and reel SN74CBTLV3857DGVR CL857
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2003, Texas Instruments Incorporated
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