SN74BCT651 Datasheet, PDF (1/10 Pages) Texas Instruments – OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

SN74BCT651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3ĆSTATE OUTPUTS
SCBS054A − AUGUST 1990 − REVISED NOVEMBER 1993
• State-of-the-Art BiCMOS Design
Significantly Reduces I_CCZ
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• Inverting Data Paths
• Power-Up High-Impedance Mode
DW OR NT PACKAGE
(TOP VIEW)
CLKAB 1
SAB 2
OEAB 3
A1 4
24 V_CC
23 CLKBA
22 SBA
21 OEBA
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
A2 5
A3 6
A4 7
A5 8
20 B1
19 B2
18 B3
17 B4
description
A6 9
16 B5
This SN74BCT651 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
A7 10
A8 11
GND 12
15 B6
14 B7
13 B8
directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.
The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.
A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four
fundamental bus-management functions that can be performed with the SN74BCT651.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.
The SN74BCT651 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OEAB
OEBA
INPUTS
CLKAB CLKBA
SAB SBA
DATA I/O
A1 THRU A8
B1 THRU B8
OPERATION OR FUNCTION
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
X
H
↑
H or L
X
X
Input
Unspecified†
H
H
↑
↑
X‡
X
Input
Output
L
X
H or L
↑
X
X
Unspecified†
Input
L
L
↑
↑
X
X‡
Output
Input
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
† _{The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,}
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
‡ _{When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus}
setup and hold times. When select control is high, clocks must be staggered in order to load both registers.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
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