SN74BCT29833 Datasheet, PDF (1/7 Pages) Texas Instruments – 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

• BiCMOS Process With TTL Inputs and
Outputs
• BiCMOS Design Reduces Standby Current
• Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
• Functionally Equivalent to SN74ALS29833
and AMD Am29833
• High-Speed Bus Transceiver With Parity
Generator/ Checker
• Parity-Error Flag With Open-Collector
Output
• Available Register For Storage of the
Parity-Error Flag
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
SN74BCT29833
8ĆBIT TO 9ĆBIT PARITY BUS TRANSCEIVER
ą
SCBS003C − SEPTEMBER 1987 − REVISED NOVEMBER 1993
DW OR NT PACKAGE
(TOP VIEW)
OEA ₁
A1 ₂
A2 ₃
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
ERR 10
CLR 11
GND 12
24 ^V_CC
23 ^B1
22 ^B2
21 B3
20 B4
19 B5
18 B6
17 B7
16 B8
15 PARITY
14 OEB
13 CLK
description
The SN74BCT29833 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error (ERR) flag. ERR is clocked into the register on the rising edge of the CLK
input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are
low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced
error condition which gives the designer more system diagnostic capability. The SN74BCT29833 provides true
logic.
The SN74BCT29833 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OEB
OEA
INPUTS
CLR
CLK
Ai
∑ of H’s
Bi†
∑ of H’s
OUTPUT AND I/O
A
B PARITY ERR‡
L
H
X
X
Odd
Even
NA
NA
A
L
H
NA
H
L
H
↑
NA
Odd
Even
B
NA
NA
H
L
X
X
L
X
X
X
X
NA
NA
H
H No↑
X
NC
H
H
L No↑
X
H
↑
Odd
X
Z
Z
Z
H
H
H
↑
Even
L
L
L
X
X
Odd
Even
NA
NA
A
H
L
NA
NA = not applicable, NC = no change, X = don’t care
† _{Summation of high-level inputs includes PARITY along with Bi inputs.}
‡ _{Output states shown assume the ERR output was previously high.}
§ _{In this mode, the ERR output, when enabled, shows inverted parity of the A bus.}
FUNCTION
A data to B bus and generate parity
B data to A bus and check parity
Clear error-flag register
Isolation§
A data to B bus and generate inverted
parity
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
2−1