SN74BCT29823_11 Datasheet, PDF (1/8 Pages) Texas Instruments – 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74BCT29823
9ĆBIT BUSĆINTERFACE FLIPĆFLOP
WITH 3ĆSTATE OUTPUTS
SCBS018D − NOVEMBER 1988 − REVISED NOVEMBER 1993
• State-of-the-Art BiCMOS Design
Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
This 9-bit bus-interface flip-flop features 3-state
outputs designed specifically for driving highly
capacitive or relatively low-impedance loads. It is
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
DW OR NT PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
9D 10
CLR 11
GND 12
24 V_CC
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 CLKEN
13 CLK
The nine flip-flops are edge-triggered D-type flip-flops. With the clock-enable (CLKEN) input low, the flip-flops
store data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching
the outputs. The SN74BCT29823 has noninverting data (D) inputs. Taking the clear (CLR) input low causes the
nine Q outputs to go low independent of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need
for interface or pullup components.
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74BCT29823 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLR CLKEN CLK D
L
L
X
X
X
L
H
L
↑
H
L
H
L
↑
L
L
H
H
X
X
H
X
X
X
X
OUTPUT
Q
L
H
L
Q0
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
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• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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