SN74AVC4T245_17 Datasheet, PDF (1/35 Pages) Texas Instruments – Dual-Bit Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

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SN74AVC4T245
SCES576G – JUNE 2004 – REVISED NOVEMBER 2014
SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation
and 3-State Outputs
1 Features
•1 Control Inputs V_IH/V_IL Levels Are Referenced to
V_CCA Voltage
• Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.2-V to 3.6-V
Power-Supply Range
• I/Os Are 4.6-V Tolerant
• I_off Supports Partial Power-Down-Mode Operation
• Maximum Data Rates
– 380 Mbps (1.8-V to 3.3-V Translation)
– 200 Mbps (< 1.8-V to 3.3-V Translation)
– 200 Mbps (Translate to 2.5 V or 1.8 V)
– 150 Mbps (Translate to 1.5 V)
– 100 Mbps (Translate to 1.2 V)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model (A114-A)
– 150-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• Personal Electronics
• Industrial
• Enterprise
• Telecom
Logic Diagram (Positive Logic)
for 1/2 of SN74AVC4T245
DIR
OE
A1
B1
A2
B2
3 Description
This 4-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The A port
is designed to track V_CCA. V_CCA accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track V_CCB. V_CCB accepts any supply voltage from
1.2 V to 3.6 V. The SN74AVC4T245 is optimized to
operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is
operational with V_CCA/V_CCB as low as 1.2 V. This
allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V,
2.5-V, and 3.3-V voltage nodes.
The SN74AVC4T245 device is designed for
asynchronous communication between two data
buses. The logic levels of the direction-control (DIR)
input and the output-enable (OE) input activate either
the B-port outputs or the A-port outputs or place both
output ports into the high-impedance mode. The
device transmits data from the A bus to the B bus
when the B-port outputs are activated, and from the B
bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is
always active and must have a logic HIGH or LOW
level applied to prevent excess I_CC and I_CCZ.
The SN74AVC4T245 device is designed so that the
control pins (1DIR, 2DIR, 1OE, and 2OE) are
supplied by V_CCA.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
The V_CC isolation feature ensures that if either V_CC
input is at GND, then both ports are in the high-
impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to V_CC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm x 3.91 mm
TVSOP (16)
3.60 mm x 4.40 mm
SN74AVC4T245 TSSOP (16)
5.00 mm x 4.40 mm
VQFN (16)
4.00 mm x 3.50 mm
UQFN (16)
2.60 mm x 1.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.