SN74AVC16835_08 Datasheet, PDF (1/17 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

D Member of the Texas Instruments
Widebus  Family
D DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D Dynamic Drive Capability Is Equivalent to
Standard Outputs With I_OH and I_OL of
±24 mA at 2.5-V V_CC
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
D Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D I_off Supports Partial-Power-Down Mode
Operation
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2 _{TA = 25°C}
2.8 ^{Process = Nominal}
2.4
2.0
VCC = 3.3 V
TA = 25°C
2.8 Process = Nominal
2.4
2.0
1.6
VCC = 2.5 V
1.2
VCC = 1.8 V
0.8
0.4
0 17 34 51 68 85 102 119 136 153 170
IOL – Output Current – mA
1.6
1.2
0.8
VCC = 3.3 V
0.4
VCC = 2.5 V
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16 0
IOH – Output Current – mA
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to
3.6-V V_CC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low
logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE
is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
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