SN74AUP2G08_16 Datasheet, PDF (1/23 Pages) Texas Instruments – LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE

SN74AUP2G08
www.ti.com
SCES681D – JANUARY 2008 – REVISED OCTOBER 2010
LOW-POWER DUAL 2-INPUT POSITIVE-AND GATE
Check for Samples: SN74AUP2G08
FEATURES
1
• Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption
(I_CC = 0.9 mA Max)
• Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot
<10% of V_CC
• I_off Supports Partial-Power-Down Mode
Operation
• Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
1A
1B
2Y
GND
DCU PACKAGE
(TOP VIEW)
1
8
2
7
3
6
4
5
V_CC
1Y
2B
2A
DQE PACKAGE
(TOP VIEW)
1A ¹
1B ²
2Y ³
GND ⁴
V 8
CC
7 _1Y
6 _2B
5 _2A
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• t_pd = 5.9 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
RSE PACKAGE
(TOP VIEW)
V_CC
1Y 1 ⁸ 7 1A
2B ²
6 _1B
YFP OR YZP PACKAGE
(TOP VIEW)
1A
1B
2Y
GND
A1 1 8 A2
B1 2 7 B2
C1 3 6 C2
D1 4 5 D2
V
CC
1Y
2B
2A
See mechanical drawings for dimensions.
2A ³ 4 ⁵ 2Y
GND
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
3.3-V
L^Lo^Vg^Cic^†
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 ^Input
Output
1.5
1
20%
20%
0%
AUP
0%
† _{Single, dual, and triple gates}
AUP
0.5
0
−0.5
0
5
10 15 20 25 30 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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