SN74AUP1G79_15 Datasheet, PDF (1/34 Pages) Texas Instruments – Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

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SN74AUP1G79
SCES592H – JULY 2004 – REVISED APRIL 2015
SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
•1 Available in the Texas Instruments NanoStar™
Package
• Low Static-Power Consumption:
I_CC = 0.9 µA Max
• Low Dynamic-Power Consumption:
C_pd = 3 pF Typ at 3.3 V
• Low Input Capacitance:
C_i = 1.5 pF Typ
• Low Noise: Overshoot and Undershoot
< 10% of V_CC
• I_off Supports Partial Power-Down-Mode Operation
• Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
• t_pd = 4 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
2 Applications
• Barcode Scanner
• Cable Solutions
• E-Book
• Embedded PC
• Field Transmitter: Temperature or Pressure
Sensor
• Fingerprint Biometrics
• HVAC: Heating, Ventilating, and Air Conditioning
• Network-Attached Storage (NAS)
• Server Motherboard and PSU
• Software Defined Radio (SDR)
• TV: High-Definition (HDTV), LCD, and Digital
• Video Communications System
• Wireless Data Access Card, Headset, Keyboard,
Mouse, and LAN Card
1
3 Description
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family ensures a very low
static and dynamic power consumption across the
entire V_CC range of 0.8 V to 3.6 V, thus resulting in an
increased battery life. The AUP devices also maintain
excellent signal integrity.
The SN74AUP1G79 is a single positive-edge-
triggered D-type flip-flop. When data at the data (D)
input meets the setup-time requirement, the data is
transferred to the Q output on the positive-going edge
of the clock pulse. Clock triggering occurs at a
voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
The SN74AUP1G79 device is fully specified for
partial-power-down applications using I_off. The I_off
circuitry disables the outputs, preventing damaging
current backflow through the device when it is
powered down.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
SOT (5)
1.60 mm × 1.20 mm
SN74AUP1G79
SON (6)
1.45 mm × 1.00 mm
SON (6)
1.00 mm × 1.00 mm
DSBGA (6)
1.16 mm × 0.76 mm
DSBGA (5)
1.39 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Power Consumption and Performance
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 ^Input
1.5
1
Output
0.5
0
−0.5
0
5
10 15 20 25 ₃₀ 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.