SN74AUP1G14_17 Datasheet, PDF (1/36 Pages) Texas Instruments – SN74AUP1G14 Low-Power Single Schmitt-Trigger Inverter

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SN74AUP1G14
SCES578J – JUNE 2003 – REVISED SEPTEMBER 2017
SN74AUP1G14 Low-Power Single Schmitt-Trigger Inverter
1 Features
•1 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
• Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
• Low Dynamic-Power Consumption
(C_pd = 4.4 pF Typical at 3.3 V)
• Low Input Capacitance (C_I = 1.5 pF Typical)
• Low Noise – Overshoot and Undershoot
<10% of V_CC
• I_off Supports Partial-Power-Down Mode Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
• t_pd = 4.9 ns Maximum at 3.3 V
2 Applications
• AV Receivers
• Smartphones
• Blu-ray Players and Home Theaters
• DVD Recorders and Players
• Desktop or Notebook PCs
• Embedded PCs
• GPS: Personal Navigation Devices
• Mobile Internet Devices
• Portable Media Players
• Smoke Detectors
• Solid State Drive (SSD): Enterprise
• High-Definition (HDTV)
• Tablets: Enterprise
• Audio Docks: Portable
• DVR and DVS
3 Description
The AUP family is TI's premier solution to the
industry's low power needs in battery-powered
portable applications. This family assures a very low
static and dynamic power consumption across the
entire V_CC range of 0.8 V to 3.6 V, resulting in an
increased battery life. This product also maintains
excellent signal integrity (see AUP – The Lowest-
Power Family and Excellent Signal Integrity).
This device functions as an independent gate with
Schmitt-trigger inputs, which allows for slow input
transition and better switching-noise immunity at the
input.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
Device Information⁽¹⁾
PART NUMBER
PACKAGE BODY SIZE (NOM)
SN74AUP1G14DBV SOT-23 (5) 2.90 mm x 1.60 mm
SN74AUP1G14DCK SC70 (5)
2.00 mm x 1.25 mm
SN74AUP1G14DRL
SOT (5)
1.60 mm x 1.20 mm
SN74AUP1G14DRY SON (6)
1.45 mm x 1.00 mm
SN74AUP1G14DSF
SON (6)
SN74AUP1G14DPW⁽²⁾ X2SON (5)
1.00 mm x 1.00 mm
0.80 mm x 0.80 mm
SN74AUP1G14YFP
DSBGA (4) 0.76 mm x 0.76 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package preview only
Logic Diagram (Positive Logic)
(DBV, DCK, DRL, DRY, DSF, DPW, and YZP
Packages)
A2
4Y
Copyright © 2017, Texas Instruments Incorporated
Logic Diagram (Positive Logic)
(YFP Package)
A1
3Y
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.