SN74AUC16374_14 Datasheet, PDF (1/13 Pages) Texas Instruments – 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• I_off Supports Partial-Power-Down Mode
Operation
• Sub-1-V Operable
• Max t_pd of 2.8 ns at 1.8 V
• Low Power Consumption, 20-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING
INFORMATION
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V V_CC, but is designed
specifically for 1.65-V to 1.95-V V_CC operation.
The SN74AUC16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403E – JULY 2002 – REVISED APRIL 2007
DGG OR DGV PACKAGE
(TOP VIEW)
1OE ¹
1Q1 ²
1Q2 ³
GND ⁴
1Q3 ⁵
1Q4 ⁶
V_CC ⁷
1Q5 ⁸
1Q6 ⁹
GND ¹⁰
1Q7 ¹¹
1Q8 ¹²
2Q1 ¹³
2Q2 ¹⁴
GND ¹⁵
2Q3 ¹⁶
2Q4 ¹⁷
V_CC ¹⁸
2Q5 ¹⁹
2Q6 ²⁰
GND ²¹
2Q7 ²²
2Q8 ²³
2OE ²⁴
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ^{(1) (2)}
ORDERABLE PART NUMBER
TSSOP – DGG
Reel of 2000
SN74AUC16374DGGR
TVSOP – DGV
Reel of 2000
SN74AUC16374DGVR
VFBGA – ZQL
Reel of 1000
SN74AUC16374ZQLR
TOP-SIDE MARKING
AUC16374
MH374
MH374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated