SN74ALVCHR16269A_14 Datasheet, PDF (1/11 Pages) Texas Instruments – 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050O – AUGUST 1995 – REVISED SEPTEMBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
• Operates From 1.65 V to 3.6 V
• Max t_pd of 5.2 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
• All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
OEA 1
OEB1 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
A3 10
GND 11
56 OEB2
55 CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 V_CC
49 2B7
48 2B8
47 2B9
46 GND
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
A4 12
A5 13
A6 14
A7 15
45 2B10
44 2B11
43 2B12
42 1B12
A8 16 41 1B11
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V_CC operation.
A9 17
GND 18
A10 19
A11 20
40 1B10
39 GND
38 1B9
37 1B8
The SN74ALVCHR16269A is used in applications in
which two ports must be multiplexed onto, or
demultiplexed from, a single port. It is particularly
suitable as an interface between synchronous
DRAMs and high-speed microprocessors.
A12 21
V_CC 22
1B1 23
1B2 24
GND 25
36 1B7
35 V_CC
34 1B6
33 1B5
32 GND
Data is stored in the internal B-port registers on the
1B3 26 31 1B4
low-to-high transition of the clock (CLK) input, when
NC 27 30 CLKENA1
the appropriate clock-enable (CLKENA) inputs are
SEL 28 29 CLK
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port. For data transfer in the B-to-A
NC − No internal connection
direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The
register on the A output permits the fastest possible data transfer, thus extending the period during which the
data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK.
Data flow is controlled by the active-low output enables (OEA, OEB1, and OEB2).
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
SSOP – DL
Tube
Tape and reel
SN74ALVCHR16269AL
SN74ALVCHR16269ALR
TSSOP – DGG
Tape and reel
SN74ALVCHR16269AGR
TVSOP – DGV
Tape and reel
SN74ALVCHR16269AVR
TOP-SIDE MARKING
ALVCHR16269A
ALVCHR16269A
VR269A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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