SN74ALVCHG162282_08 Datasheet, PDF(1/12 Page) Texas Instruments – 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SN74ALVCHG162282_08 Datasheet, PDF (1/12 Pages) Texas Instruments – 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

www.ti.com

FEATURES

â¢ Member of the Texas Instruments Widebusâ¢

Family

â¢ EPICâ¢ (Enhanced-Performance Implanted

CMOS) Submicron Process

â¢ A-Port Outputs Have Equivalent 50-â¦ Series

Resistors and B-Port Outputs Have Equivalent

20-â¦ Series Resistors, So No External

Resistors Are Required

â¢ ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

â¢ Latch-Up Performance Exceeds 250 mA Per

JESD 17

â¢ Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

â¢ Packaged in Thin Very Small-Outline Package

NOTE: For order entry, the DBB package is abbreviated to G. For

tape and reel, the DBBR package is abbreviated to GR.

DESCRIPTION

The SN74ALVCHG162282 is an 18-bit to 36-bit

registered bus exchanger. This device is intended for

use in applications where data must be transferred

from a narrow high-speed bus to a wide

lower-frequency bus. It is designed specifically for

low-voltage (3.3-V) VCC operation.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input. For data transfer in the B-to-A direction,

the select (SEL) input selects 1B or 2B data for the A

outputs.

For data transfer in the A-to-B direction, a two-stage

pipeline is provided in the 1B path, with a single

storage register in the 2B path. Data flow is controlled

by the active-low output-enable (OE) and

direction-control (DIR) input. DIR is registered to

synchronize the bus direction changes with the clock.

SN74ALVCHG162282

18-BIT TO 36-BIT REGISTERED BUS EXCHANGER

WITH 3-STATE OUTPUTS

SCES094D â FEBRUARY 1997 â REVISED OCTOBER 2004

DBB PACKAGE

(TOP VIEW)

VCC 1

GND 2

2B9 3

1B9 4

2B8 5

GND 6

1B8 7

2B7 8

1B7 9

VCC 10

2B6 11

1B6 12

2B5 13

1B5 14

GND 15

2B4 16

1B4 17

2B3 18

1B3 19

VCC 20

GND 21

2B2 22

1B2 23

2B1 24

1B1 25

VCC 26

A1 27

A2 28

A3 29

GND 30

A4 31

A5 32

A6 33

VCC 34

A7 35

A8 36

A9 37

GND 38

CLK 39

SEL 40

80 VCC

79 GND

78 1B10

77 2B10

76 1B11

75 GND

74 2B11

73 1B12

72 2B12

71 VCC

70 1B13

69 2B13

68 1B14

67 2B14

66 GND

65 1B15

64 2B15

63 1B16

62 2B16

61 VCC

60 GND

59 1B17

58 2B17

57 1B18

56 2B18

55 VCC

54 A18

53 A17

52 A16

51 GND

50 A15

49 A14

48 A13

47 VCC

46 A12

45 A11

44 A10

43 GND

42 OE

41 DIR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

▷