SN74ALVCH32374_13 Datasheet, PDF (1/12 Pages) Texas Instruments – 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES283D – OCTOBER 1999 – REVISED AUGUST 2004
FEATURES
• Member of the Texas Instruments Widebus+™
Family
• Operates From 1.65 V to 3.6 V
• Max t_pd of 4.2 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On
the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data
(D) inputs. The output-enable (OE) input can be used to place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive
bus lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER TOP-SIDE MARKING
LFBGA - GKE
LFBGA - ZKE (Pb-free)
Tape and reel
SN74ALVCH32374KR
74ALVCH32374ZKER
ACH374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK
D
L
↑
H
L
↑
L
L H or L X
H
X
X
OUTPUT
Q
H
L
Q₀
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated