SN74ALVCH16823_15 Datasheet, PDF (1/20 Pages) Texas Instruments – 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 18-bit bus-interface flip-flop is designed for
1.65-V to 3.6-V V_CC operation.
The SN74ALVCH16823 features 3-state outputs
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The SN74ALVCH16823 can be used as two 9-bit
flip-flops or one 18-bit flip-flop. With the clock-enable
(CLKEN) input low, the D-type flip-flops enter data on
the low-to-high transitions of the clock. Taking
CLKEN high disables the clock buffer, thus latching
the outputs. Taking the clear (CLR) input low causes
the Q outputs to go low independently of the clock.
SN74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES038F – JULY 1995 – REVISED APRIL 2005
DGG OR DL PACKAGE
(TOP VIEW)
1CLR ¹
1OE ²
1Q1 ³
GND ⁴
1Q2 ⁵
1Q3 ⁶
V_CC ⁷
1Q4 ⁸
1Q5 ⁹
1Q6 ¹⁰
GND ¹¹
1Q7 ¹²
1Q8 ¹³
1Q9 ¹⁴
2Q1 ¹⁵
2Q2 ¹⁶
2Q3 ¹⁷
GND ¹⁸
2Q4 ¹⁹
2Q5 ²⁰
2Q6 ²¹
V_CC ²²
2Q7 ²³
2Q8 ²⁴
GND ²⁵
2Q9 ²⁶
2OE ²⁷
2CLR ²⁸
56 _1CLK
55 _1CLKEN
54 _1D1
53 _GND
52 _1D2
51 _1D3
50 _VCC
49 _1D4
48 _1D5
47 _1D6
46 _GND
45 _1D7
44 _1D8
43 _1D9
42 _2D1
41 _2D2
40 _2D3
39 _GND
38 _2D4
37 _2D5
36 _2D6
35 _VCC
34 _2D7
33 _2D8
32 _GND
31 _2D9
30 _2CLKEN
29 _2CLK
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16823 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2005, Texas Instruments Incorporated