SN74ALVCH16721_08 Datasheet, PDF (1/16 Pages) Texas Instruments – 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
This 20-bit flip-flop is designed specifically for 1.65-V
to 3.6-V V_CC operation.
The 20 flip-flops of the SN74ALVCH16721 are
edge-triggered D-type flip-flops with qualified clock
storage. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs if
the clock-enable (CLKEN) input is low. If CLKEN is
high, no data is stored.
A buffered output-enable (OE) input places the 20
outputs in either a normal logic state (high or low) or
the high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without
need for interface or pullup components. OE does not
affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the
outputs are in the high-impedance state.
SN74ALVCH16721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES052E – JULY 1995 – REVISED AUGUST 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OE ¹
Q1 ²
Q2 ³
GND ⁴
Q3 ⁵
Q4 ⁶
V_CC ⁷
Q5 ⁸
Q6 ⁹
Q7 ¹⁰
GND ¹¹
Q8 ¹²
Q9 ¹³
Q10 ¹⁴
Q11 ¹⁵
Q12 ¹⁶
Q13 ¹⁷
GND ¹⁸
Q14 ¹⁹
Q15 ²⁰
Q16 ²¹
V_CC ²²
Q17 ²³
Q18 ²⁴
GND ²⁵
Q19 ²⁶
Q20 ²⁷
NC ²⁸
56 CLK
55 D1
54 _D2
53 GND
52 D3
51 D4
50 V_CC
49 _D5
48 _D6
47 _D7
46 GND
45 D8
44 D9
43 _D10
42 _D11
41 _D12
40 _D13
39 GND
38 _D14
37 _D15
36 _D16
35 _VCC
34 _D17
33 _D18
32 _GND
31 _D19
30 _D20
29 _CLKEN
NC − No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16721 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated