SN74ALVCH16646_08 Datasheet, PDF (1/18 Pages) Texas Instruments – 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

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SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032F – JULY 1995 – REVISED SEPTEMBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
1DIR 1
1CLKAB 2
1SAB 3
GND 4
1A1 5
1A2 6
V_CC 7
1A3 8
1A4 9
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
56 1OE
55 1CLKBA
54 1SBA
53 GND
52 1B1
51 1B2
50 V_CC
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
DESCRIPTION
2A1 15
2A2 16
42 2B1
41 2B2
This 16-bit bus transceiver and register is designed
for 1.65-V to 3.6-V V_CC operation.
The SN74ALVCH16646 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A
or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four
fundamental bus-management functions that can be
performed with the SN74ALVCH16646.
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
V_CC 22
2A7 23
2A8 24
GND 25
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
35 V_CC
34 2B7
33 2B8
32 GND
Output-enable (OE) and direction-control (DIR) inputs
2SAB 26 31 2SBA
are provided to control the transceiver functions. In
2CLKAB 27 30 2CLKBA
the transceiver mode, data present at the
2DIR 28 29 2OE
high-impedance port may be stored in either register
or in both. The select-control (SAB and SBA) inputs
can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in
one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16646 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated