SN74ALVCH162841_09 Datasheet, PDF (1/15 Pages) Texas Instruments – 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74ALVCH162841
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES088E – OCTOBER 1996 – REVISED SEPTEMBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
DESCRIPTION
This 20-bit bus-interface D-type latch is designed for
1.65-V to 3.6-V V_CC operation.
The SN74ALVCH162841 features 3-state outputs
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The SN74ALVCH162841 can be used as two 10-bit
latches or one 20-bit latch. The 20-bit latch is a
transparent D-type latch. The device has noninverting
data (D) inputs and provides true data at its outputs.
While the latch-enable (1LE or 2LE) input is high, the
Q outputs of the corresponding 10-bit latch follow the
D inputs. When LE is taken low, the Q outputs are
latched at the levels set up at the D inputs.
DGG OR DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 8
1Q6 9
1Q7 10
GND 11
1Q8 12
1Q9 13
1Q10 14
2Q1 15
2Q2 16
2Q3 17
GND 18
2Q4 19
2Q5 20
2Q6 21
V_CC 22
2Q7 23
2Q8 24
GND 25
2Q9 26
2Q10 27
2OE 28
56 1LE
55 1D1
54 1D2
53 GND
52 1D3
51 1D4
50 V_CC
49 1D5
48 1D6
47 1D7
46 GND
45 1D8
44 1D9
43 1D10
42 2D1
41 2D2
40 2D3
39 GND
38 2D4
37 2D5
36 2D6
35 V_CC
34 2D7
33 2D8
32 GND
31 2D9
30 2D10
29 2LE
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A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2004, Texas Instruments Incorporated