SN74ALVCH162721_08 Datasheet, PDF (1/14 Pages) Texas Instruments – 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055G – DECEMBER 1995 – REVISED SEPTEMBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
DESCRIPTION
This 20-bit flip-flop is designed for low-voltage 1.65-V
to 3.6-V V_CC operation.
The 20 flip-flops of the SN74ALVCH162721 are
edge-triggered D-type flip-flops with qualified clock
storage. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs if
the clock-enable (CLKEN) input is low. If CLKEN is
high, no data is stored.
DGG OR DL PACKAGE
(TOP VIEW)
OE 1
Q1 2
Q2 3
GND 4
Q3 5
Q4 6
V_CC 7
Q5 8
Q6 9
Q7 10
GND 11
Q8 12
Q9 13
Q10 14
Q11 15
Q12 16
Q13 17
GND 18
Q14 19
Q15 20
Q16 21
V_CC 22
Q17 23
Q18 24
GND 25
Q19 26
Q20 27
NC 28
56 CLK
55 D1
54 D2
53 GND
52 D3
51 D4
50 V_CC
49 D5
48 D6
47 D7
46 GND
45 D8
44 D9
43 D10
42 D11
41 D12
40 D13
39 GND
38 D14
37 D15
36 D16
35 V_CC
34 D17
33 D18
32 GND
31 D19
30 D20
29 CLKEN
A buffered output-enable (OE) input places the 20
outputs in either a normal logic state (high or low
NC − No internal connection
level) or the high-impedance state. In the
high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components. OE
does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
The SN74ALVCH162721 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated