SN74ALVCH16270_08 Datasheet, PDF (1/15 Pages) Texas Instruments – 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES028G – JULY 1995 – REVISED AUGUST 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
DGG OR DL PACKAGE
(TOP VIEW)
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVCH16270 is used in applications in
which data must be transferred from a narrow
high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the internal
registers on the low-to-high transition of the clock
(CLK) input when the appropriate CLKEN inputs are
low. The select (SEL) line selects 1B or 2B data for
the A outputs. For data transfer in the A-to-B
direction, a two-stage pipeline is provided in the
A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of the CLKENA inputs
allows two sequential 12-bit words to be presented
synchronously as a 24-bit word on the B port. Data
flow is controlled by the active-low output enables
(OEA, OEB). The control terminals are registered to
synchronize the bus-direction changes with CLK.
OEA 1
CLKEN1B 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
V_CC 22
1B1 23
1B2 24
GND 25
1B3 26
CLKEN2B 27
SEL 28
56 _OEB
55 _CLKENA2
54 _2B4
53 _GND
52 _2B5
51 _2B6
50 _VCC
49 _2B7
48 _2B8
47 _2B9
46 _GND
45 _2B10
44 _2B11
43 _2B12
42 _1B12
41 _1B11
40 _1B10
39 _GND
38 _1B9
37 _1B8
36 _1B7
35 _VCC
34 _1B6
33 _1B5
32 _GND
31 _1B4
30 _CLKENA1
29 _CLK
line
space
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as
possible, and OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the
outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated