SN74ALVCH162334_09 Datasheet, PDF (1/15 Pages) Texas Instruments – 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

www.ti.com
FEATURES
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
• Designed to Comply With JEDEC 168-Pin and
200-Pin SDRAM Buffered DIMM Specification
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), and Thin Very Small-Outline (DGV)
Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR, and the DGVR package is abbreviated
to VR.
DESCRIPTION
This 16-bit universal bus driver is designed for 1.65-V
to 3.6-V V_CC operation.
SN74ALVCH162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES120H – JULY 1997 – REVISED SEPTEMBER 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
OE 1
Y1 2
Y2 3
GND 4
Y3 5
Y4 6
V_CC 7
Y5 8
Y6 9
GND 10
Y7 11
Y8 12
Y9 13
Y10 14
GND 15
Y11 16
Y12 17
V_CC 18
Y13 19
Y14 20
GND 21
Y15 22
Y16 23
NC 24
48 CLK
47 A1
46 A2
45 GND
44 A3
43 A4
42 V_CC
41 A5
40 A6
39 GND
38 A7
37 A8
36 A9
35 A10
34 GND
33 A11
32 A12
31 V_CC
30 A13
29 A14
28 GND
27 A15
26 A16
25 LE
NC − No internal connection
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at
a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162334 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated