SN74ALVCF162834 Datasheet, PDF (1/14 Pages) Texas Instruments – 3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCF162834
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES409B – AUGUST 2002 – REVISED OCTOBER 2004
FEATURES
• Member of the Texas Instruments Widebus™
Family
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
• Ideal for Use in PC133 Register DIMM
• Typical Output Skew . . . <250 ps
• V_CC = 3.3 V ± 0.3 V . . . Normal Range
• V_CC = 2.7 V to 3.6 V . . . Extended Range
• V_CC = 2.5 V ± 0.2 V
• Rail-to-Rail Output Swing for Increased Noise
Margin
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
V_CC 7
Y4 8
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 V_CC
49 A4
• Balanced Output Drivers . . . ±18 mA
• Low Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Y11 16
Y12 17
GND 18
41 A11
40 A12
39 GND
DESCRIPTION/ORDERING INFORMATION
Y13 19 38 A13
This 18-bit universal bus driver is designed for
2.3-V to 3.6-V V_CC operation.
Data flow from A to Y is controlled by the
Y14 20
Y15 21
V_CC 22
Y16 23
37 A14
36 A15
35 V_CC
34 A16
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
low. When LE is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
Y17 24
GND 25
Y18 26
OE 27
LE 28
33 A17
32 GND
31 A18
30 CLK
29 GND
the outputs are in the high-impedance state.
NC − No internal connection
The ALVCF162834 has series damping resistors in the device output structure that reduce switching noise in
128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive
between the ALVC162834 (±12 mA) and ALVC16834 (±24 mA).
The SN74ALVCF162834 is a faster version of the SN74ALVC162834. It is suitable for PC133 applications,
particularly for SDRAM modules clocked at 133 MHz.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
SSOP - DL
Tube
Tape and reel
SN74ALVCF162834DL
SN74ALVCF162834DLR
TSSOP - DGG
Tape and reel
SN74ALVCF162834GR
TVSOP - DGV
Tape and reel
SN74ALVCF162834VR
TOP-SIDE MARKING
ALVCF162834
ALVCF162834
VF162834
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated