SN74ALVC16721 Datasheet, PDF (1/8 Pages) Texas Instruments – 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVC16721
3.3ĆV 20ĆBIT FLIPĆFLOP
WITH 3ĆSTATE OUTPUTS
SCAS267A − MARCH 1993 − REVISED MAY 1995
D Member of the Texas Instruments
Widebus  Family
DGG OR DL PACKAGE
(TOP VIEW)
D EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Bus Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
OE 1
Q1 2
Q2 3
GND 4
Q3 5
Q4 6
V_CC 7
Q5 8
Q6 9
Q7 10
GND 11
Q8 12
56 CLK
55 D1
54 D2
53 GND
52 D3
51 D4
50 V_CC
49 D5
48 D6
47 D7
46 GND
45 D8
Shrink Small-Outline (DL) and Thin Shrink
Q9 13 44 D9
Small-Outline (DGG) Packages
Q10 14 43 D10
description
Q11 15
Q12 16
42 D11
41 D12
This 20-bit flip-flop is designed specifically for
low-voltage (3.3-V) V_CC operation; it is tested at
2.5-V, 2.7-V, and 3.3-V V_CC.
Q13 17
GND 18
Q14 19
Q15 20
40 D13
39 GND
38 D14
37 D15
The SN74ALVC16721’s 20 flip-flops are edge-
Q16 21 36 D16
triggered D-type flip-flops with qualified clock
storage. On the positive transition of the clock
V_CC 22
Q17 23
35 V_CC
34 D17
(CLK) input, the device provides true data at the
Q outputs if the clock-enable (CLKEN) input is low.
If CLKEN is high, no data is stored.
Q18 24
GND 25
Q19 26
33 D18
32 GND
31 D19
A buffered output-enable (OE) input places the
20 outputs in either a normal logic state (high
Q20 27
NC 28
30 D20
29 CLKEN
or low level) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive
bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74ALVC16721 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16721 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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