SN74ALVC16269 Datasheet, PDF (1/9 Pages) Texas Instruments – 12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74ALVC16269
12ĆBIT TO 24ĆBIT REGISTERED BUS TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCAS417B − OCTOBER 1993 − REVISED JULY 1995
D EPIC  ( Enhanced-Performance Implanted
CMOS) Submicron Process
DGG OR DL PACKAGE
(TOP VIEW)
D Member of the Texas Instruments
Widebus  Family
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Bus Hold on Data Inputs Eliminates
the Need for External Pullup/ Pulldown
Resistors
D Package Options Include Plastic Shrink
OEA 1
OEB1 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
A3 10
GND 11
A4 12
56 OEB2
55 CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 V_CC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
Small-Outline (DL) and Thin Shrink
A5 13 44 2B11
Small-Outline (DGG) Packages
A6 14 43 2B12
description
A7 15
A8 16
42 1B12
41 1B11
The SN74ALVC16269 is a 12-bit to 24-bit
registered bus transceiver, which is intended
for applications where two separate ports
must be multiplexed onto, or demultiplexed
from, a single port. The device is particularly
suitable as an interface between synchronous
DRAMs and high-speed microprocessors. The
SN74ALVC16269 is designed specifically for
low-voltage (3.3-V ) V_CC operation; it is tested at
2.5-V, 2.7-V, and 3.3-V V_CC.
Data is stored in the internal B-port registers on
the low-to-high transition of the clock (CLK) input
A9 17
GND 18
A10 19
A11 20
A12 21
V_CC 22
1B1 23
1B2 24
GND 25
1B3 26
NC 27
SEL 28
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 V_CC
34 1B6
33 1B5
32 GND
31 1B4
30 CLKENA1
29 CLK
when the appropriate clock-enable (CLKENA)
NC − No internal connection
inputs are low. Proper control of these inputs
allows two sequential 12-bit words to be
presented as a 24-bit word on the B port. For data
transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data
for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the
period that the data is valid on the bus. The control terminals are registered so that all transactions are
synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16269 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16269 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
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