SN74ALVC162601 Datasheet, PDF (1/9 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74ALVC162601
18ĆBIT UNIVERSAL BUS TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCAS376 − MARCH 1994
• Member of the Texas Instruments
Widebus  Family
• UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
• EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
• Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors on All I/O Pins
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit universal bus transceiver is designed
for 2.7-V to 3.6-V V_CC operation.
The SN74ALVC162601 combines D-type latches
and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held
at a high or low logic level. If LEAB is low, the A-bus
data is stored in the latch/flip-flop on the
high-to-low transition of CLKAB. Output enable
OEAB is active low. When OEAB is low, the
outputs are active. When OEAB is high, the
outputs are in the high-impedance state.
DGG OR DL PACKAGE
(TOP VIEW)
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
V_CC 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V_CC 22
A16 23
A17 24
GND 25
A18 26
OEBA 27
LEBA 28
56 CLKENAB
55 CLKAB
54 B1
53 GND
52 B2
51 B3
50 V_CC
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 V_CC
34 B16
33 B17
32 GND
31 B18
30 CLKBA
29 CLKENBA
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs, include 25-Ω series resistors to reduce overshoot and undershoot.
The SN74ALVC162601 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN74ALVC162601 is characterized for operation from − 40°C to 85°C.
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright  1994, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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